Conventional shift registers generally used three or more input/output (signal) pins to interface to a shift register. FIG. 1 illustrates such a shift register 10. The shift register 10 receives a clock signal CLK at input 12 from a clock pin CLK and a data in signal DIN at input 14 from a data in pin DIN. The shift register 10 generates a data out signal DOUT at output 16, which interfaces with external circuits through a data output pin DOUT. As a result, the shift register 10 generally uses all three separate pins to program a register. When only one signal pin is available for interfacing to the programming register requiring three signal pins is not allowed. Other limited pin devices may also find supporting three signal pins for programming an undesirable design constraint.
FIG. 2 illustrates an alternate shift register 20. The shift register 20 generally comprises an input 22 that receives a clock signal CLK, an input 24 that receives a data input signal DIN and an output 26 that presents a data output signal DOUT. The data output signal DOUT is coupled to the data input 24 through a buffer 28. The output 26 and the input 24 are coupled to a data input/output pin DI/O. The input 22 is coupled to a clock pin CLK. The buffer 28 is also coupled to a read/write pin R/W which receives a read/write signal that places the shift register 20 in either a read or write mode. The shift register 20 provides a bidirectional input/output pin DI/O but still uses three pins for operation.
Both the shift register 10 and the shift register 20 generally use three pins to interface for proper programming. As a result, a device having a limited pin count, such as a four pin device, which during programming has only one signal pin available (Vdd pin, Vss pin, Vpp programming voltage pin, signal pin) require a one pin shift register interface which combines clock and data functions.